The present disclosure generally relates to semiconductor apparatuses and manufacturing processes, and more particularly, relates to processes for high aspect ratio gap fill.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is needed to accommodate the increasing density of circuits necessary for today's semiconductor products. As memory devices, such as dynamic random access memory (DRAM), are scaled down in size, various aspects of manufacturing DRAM integrated circuits are becoming more challenging. For example, extreme aspect ratios (the ratio of the vertical depth of a trench to the horizontal width) in small-scale devices present etch and deposition process challenges.
Insulating materials, for example, SiO2, are used to isolate conductors and other active regions in semiconductor devices. In prior art back-end-of-line (BEOL) applications, e.g., insulation for metal lines, a plasma enhanced chemical vapor deposition (PECVD) process based on a tetraethoxysilane (TEOS) source precursor was typically used for the deposition of insulating material, which resulted in an isotropic or conformal deposition profile. An anisotropic etch was then used, such as a physical sputter etch, to remove the insulating material overhangs that covered areas that needed to be filled, and another insulating layer was deposited, e.g., by PECVD. A technique used to deposit insulators that is being used more frequently in densely-packed semiconductor devices having small feature sizes and high aspect ratios is high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD has been used in the BEOL in the past, and is also being used in the front-end-of-line (FEOL), for shallow trench isolation (STI). Generally, the HDP-CVD ions and electrons are generated in an inductively coupled radiofrequency (RF) plasma (no electrode in non-capacitively coupled plasmas). An RF biasing power is applied to another (substrate-holding) electrode to create a significant ion bombardment (i.e., sputter etching) component during deposition. For gap filling, HPD-CVD processes provide simultaneous deposition and etching in which loosely deposited films or “deposited species” over planar to topographical surface are sputtered off by reactive ions and radicals during deposition. In this manner, voids can be eliminated during the gap full process. However, HDP-CVD is proving a challenge with today's rapidly increasing high aspect ratio features, which are approaching 4:1 and higher.
Several commercial HPD-CVD systems have been developed in connection with efforts to advance the integrated circuit technology to the ultra-large scale integration (ULSI) level. These systems use either electron cyclotron resonance (ECR) or inductively coupled plasma (ICP) sources for high-density plasma generation. Current HDP-CVD processes generally employ the use of a relatively low pressure (about 2 to about 10 mTorr range) to achieve a high electron density (1010 to 1012 cm3) and a high fractional ionization rate (10−4 to 10−1). In order to achieve a significant deposition rate while maintaining a reasonably high sputter-etching rate for gap-filling purposes, a significant amount of initial reactant (i.e., deposited species in the plasma) must flow through the reactor, but the system is typically kept at low pressure (less than 10 mTorr) constantly during deposition. As a result, the required vacuum system must have a high pumping capability throughput and robustness. It must withstand the high temperature and high reactivity of the reaction by-products while removing them at a high rate. For an HDP CVD system, an advanced turbomolecular pump is generally used to achieve a suitable deposition rate (at low pressure) and maintain acceptable pumping reliability.
FIG. 1 illustrates a prior art semiconductor device 10 having isolation trenches 11 formed in a substrate 12, the isolation trenches 11 having a relatively high aspect ratio. The aspect ratio refers to the ratio of the height (h) compared to the width (w) between the isolation trenches 11, and is expressed as a ratio of h:w, e.g., 3:1 or 4:1.
The semiconductor device 10 in this example comprises a DRAM device, where the trenches 11 comprise isolation trenches (IT's) that are adapted to electrically isolate element regions of a DRAM chip, for example. The element regions may comprise active areas, storage capacitors, transistors, and other electronic elements, as examples. The process of forming IT's is often also referred to in the art as shallow trench isolation (STI), for example.
Prior to formation of the isolation trenches 11 within the substrate 12, a pad nitride 14 may be deposited over the substrate 12. An insulating layer 16 is deposited over the semiconductor wafer 10 using HPD-CVD to fill the trenches between the active areas, as shown. Because of the high aspect ratio h:w, which may be 2:1 or greater, the HDP-CVD process may result in voids 20 that form within the trenches 11, as shown. This occurs because an insulator 16 deposited by HDP-CVD has a tendency to form cusps or huts 18 at the vicinity of the top portion of the trenches 11. This results in a greater thickness of the insulating layer 16 on the sidewall at the top of the trenches 11 compared to the sidewall deposition in the lower portion of the trenches 11. As a result, the top of the insulating layer 16 nearer the huts 18 closes, preventing the void regions 20 from being filled. The insulating layer 16 peaks ‘pinch’ the flow of insulating material 16 reactants into the trenches 11.
A problem in prior art isolation techniques is the formation of these voids 20 in high-aspect ratio trenches, especially as design rules for advanced integrated circuits require smaller dimensions. As previously noted, aspect ratios in DRAM devices are approaching 4:1 and greater. Moreover, as the minimum feature size is made smaller, the oxide gap fill of isolation trenches 11 becomes more challenging, especially in devices such as vertical DRAMs. Leaving voids 20 in a finished semiconductor device may result in device 10 failures. Voids 20 may inadvertently be filled with conductive material in subsequent processing steps such as gate conductor deposition, for example, which may short elements in the substrate.
Accordingly, there remains a need in the art for improved processes for gap filling high aspect ratio structures without forming voids or cusps during the deposition process.